module IS_reg
	#(parameter length = 16)
	(
		input clk,
		input rst_n,

		input signed [length-1:0] input_signal,

		output reg signed [length-1:0] IS0,
		output reg signed [length-1:0] IS1,
		output reg signed [length-1:0] IS2,
		output reg signed [length-1:0] IS3,
		output reg signed [length-1:0] IS4,
		output reg signed [length-1:0] IS5,
		output reg signed [length-1:0] IS6,
		output reg signed [length-1:0] IS7,
		output reg signed [length-1:0] IS8,
		output reg signed [length-1:0] IS9,
		output reg signed [length-1:0] IS10,
		output reg signed [length-1:0] IS11,
		output reg signed [length-1:0] IS12,
		output reg signed [length-1:0] IS13,
		output reg signed [length-1:0] IS14,
		output reg signed [length-1:0] IS15,
		output reg signed [length-1:0] IS16,
		output reg signed [length-1:0] IS17,
		output reg signed [length-1:0] IS18,
		output reg signed [length-1:0] IS19,
		output reg signed [length-1:0] IS20,
		output reg signed [length-1:0] IS21,
		output reg signed [length-1:0] IS22,
		output reg signed [length-1:0] IS23,
		output reg signed [length-1:0] IS24,
		output reg signed [length-1:0] IS25,
		output reg signed [length-1:0] IS26,
		output reg signed [length-1:0] IS27,
		output reg signed [length-1:0] IS28,
		output reg signed [length-1:0] IS29,
		output reg signed [length-1:0] IS30,
		output reg signed [length-1:0] IS31
	);

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS0 <= 0;
	end 
	else begin
		IS0 <= input_signal;
	end 
end 

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS1 <= 0;
	end
	else begin
		IS1 <= IS0;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS2 <= 0;
	end
	else begin
		IS2 <= IS1;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS3 <= 0;
	end
	else begin
		IS3 <= IS2;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS4 <= 0;
	end
	else begin
		IS4 <= IS3;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS5 <= 0;
	end
	else begin
		IS5 <= IS4;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS6 <= 0;
	end
	else begin
		IS6 <= IS5;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS7 <= 0;
	end
	else begin
		IS7 <= IS6;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS8 <= 0;
	end
	else begin
		IS8 <= IS7;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS9 <= 0;
	end
	else begin
		IS9 <= IS8;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS10 <= 0;
	end
	else begin
		IS10 <= IS9;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS11 <= 0;
	end
	else begin
		IS11 <= IS10;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS12 <= 0;
	end
	else begin
		IS12 <= IS11;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS13 <= 0;
	end
	else begin
		IS13 <= IS12;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS14 <= 0;
	end
	else begin
		IS14 <= IS13;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS15 <= 0;
	end
	else begin
		IS15 <= IS14;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS16 <= 0;
	end
	else begin
		IS16 <= IS15;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS17 <= 0;
	end
	else begin
		IS17 <= IS16;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS18 <= 0;
	end
	else begin
		IS18 <= IS17;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS19 <= 0;
	end
	else begin
		IS19 <= IS18;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS20 <= 0;
	end
	else begin
		IS20 <= IS19;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS21 <= 0;
	end
	else begin
		IS21 <= IS20;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS22 <= 0;
	end
	else begin
		IS22 <= IS21;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS23 <= 0;
	end
	else begin
		IS23 <= IS22;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS24 <= 0;
	end
	else begin
		IS24 <= IS23;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS25 <= 0;
	end
	else begin
		IS25 <= IS24;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS26 <= 0;
	end
	else begin
		IS26 <= IS25;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS27 <= 0;
	end
	else begin
		IS27 <= IS26;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS28 <= 0;
	end
	else begin
		IS28 <= IS27;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS29 <= 0;
	end
	else begin
		IS29 <= IS28;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS30 <= 0;
	end
	else begin
		IS30 <= IS29;
	end
end

always @(posedge clk or negedge rst_n) begin
	if (~rst_n)begin
		IS31 <= 0;
	end
	else begin
		IS31 <= IS30;
	end
end

endmodule